6. Consider a multi-core processor using 3-state MSI protocol. If one of the cache block is in S state , what will be the state(s) of the same cache block in
I or II or III
II or III
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7. Suppose an application is running on a 64-processor multiprocessor, which
takes 300 cycles to handle reference to a remote memory. If the base CPI is 0.5,
how much faster is the multiprocessor if there is no communication versus if 0.3%
of the instructions involve a remote communication reference?
8. Consider a multi-core processor using 3-state MSI protocol. Assume
that a cache block is shared across all cores. After some time, one of the cores
changes the state of the cache block from ‘S’ to ‘M’, what will be the state(s) of
the cache block in other cores?
9. Necessary conditions for cache coherency to satisfy is/are
Program order for memory operations.
10. Consider a multicore processor using directory based MSI protocol. One
of the cache block is in ‘M’ state. Due to cache replacement, this block is chosen
as a victim. What is the next course of action?
No state transition. Sharers list in home node is unmodified.
Sharers list in home node is modified to null. State transition to I state.
The current processor id is removed from sharers list in home node. No
State transition to I. Sharers list in home node is unmodified.
UGC NET PAPER 1
UGC NET Management
UGC NET COMPUTER SCIENCE
UGC NET COMMERCE
GATE COMPUTER SCIENCE
CFA Level 1
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