Explanation : The 7 mutually exclusive signals can be encoded in ceiling(log2 7) = 3 bits, while the remaining 13 signals will remain un-encoded. So the number of bits in a control word will be 3 + 13 = 16.
Explanation : For horizontal encoding, one bit is used for each control signal; therefore, we shall require 126 control signals. For vertical encoding, the 126 control signals can be encoded in ceiling(log2 126) = 7 bits.
Explanation : In MIPS32 architecture, two register operands are prefetched during the
ID stage, which required two read ports in the register bank. Also, for
pipelined implementation, a register write can occur during WB. Thus
two read and one write ports are required in the register bank.