# Computer System Architecture - Digital Logic Circuits - Combinational Circuits

>>>>>>>>Digital Logic Circuits - Combinational Circuits

• A

NOR  • B

AND  • C

OR  • D

NAND  • Option : C
• Explanation : In OR gate we need atleast one bit to be equal to 1 to generate the output as 1 because OR means any of the condition out of two is equal to 1 which means if atleast one input is 1 then it shows output as 1 . Number of 1's in input may be more than one but the output will always be 1 in OR gate. So the answer is 'C'.

• A

Rise time  • B

Decay time  • C

Propagation time  • D

Charging time  • A

Rise time  • B

Decay time  • C

Propagation time  • D

Operating speed  • A

Operating speed  • B

Propagation speed  • C

Binary level transaction period  • D

Charging time  • A

one  • B

two  • C

three  • D

four  • Option : C
• Explanation : Y=A+B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also write After 1st NAND operation Y = (A AND B)' Y= A' + B' (Demorgan's Law) After 2nd NAND operation Y= ( A' + B')' Y= A . B (Demorgan's Law) After 3rd NAND operation Y= ( A . B )' Y= A' + B ' (Demorgan's Law) So we need 3 NAND gates.

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