UGC NET COMPUTER SCIENCE SOLVED PAPERS 2014-16 - UGC NET Computer Science Paper 3 December 2015

1. The three outputs x1x2x3 from the 8 X 3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority ?

  • Option : B
  • Explanation :
    The priority preference for 8 X 3 priority encoder will be:
    000 First
    001 Second
    010 Third
    011 Fourth
    100 Fifth
    101 Sixth
    110 Seventh
    111 Eighth
    According to question second highest priority vector address will be 10100100. i.e. 1010 0100. When we convert it to hexadecimal then it will be A4. So, option (B) is correct.
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2. What will be the output at PORT1 if the following program is executed ?
MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT

  • Option : B
  • Explanation :
    In 8085 programming, the result of an operation is stored in the accumulator. So output is 82H.
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3. Which of the following 8085 microprocessor hardware interrupt has the lowest priority?

  • Option : D
  • Explanation :
    8085 microprocessor has 5 hardware interrupts. Named TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. The above order is decreasing in priority. So, option (D) is correct.
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4. A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?

  • Option : D
  • Explanation :
    Memory cycle time = 250 nsec memory is refreshed 32 times per msec i.e. Number of refreshes in 1 memory cycle (i.e in 250 nsec) = (32 * 250 * 10-9) / 10-3 = 8 * 10-3. Time taken for each refresh = 100 nsec Time taken for 8 * 10-3 refreshes = 8 * 10-3 * 100 * 10-9. = 8 * 10-10 Percentage of the memory cycle time used for refreshing : = (Time taken to refresh in 1 memory cycle / Total time) * 100 = (8 * 10-10 / 250 * 10-9) * 100 = 0.032 * 10 = 0.32 So, option (D) is correct.
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5. A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

  • Option : B
  • Explanation :
    DMA controller transfers 32 bit(4 byte) words to memory(cycle stealing mode). Device transmits 4800 character per second (1 character = i byte) So, for 1 byte it will take 1 / 4800 sec. Since the controller transfers 4 byte in cycle stealing mode, it will take 4 * (1 / 4800) = 1 / 1200 sec. i.e. 1200 character will be transfered in cycle stealing mode and it is given that CPU is fetching and executing instructions at an average rate of one million instructions per second. slow down or cycle wasted % in DMA transfer = ( 1200 / 1000000) * 100 = 0.12 % So, option (B) is correct.
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